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PCI EXPRESS NEWS - September 2008Welcome to PLX's PCIe News. Thank you for subscribing. If you can not read this email, please view it on the Web. |
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In this issue:
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DMA Engine Inside New PCIe Switches
PEX 8619 (16 lane, 16 port), PEX 8615 (12 lane, 12 port) and PEX 8609 (eight lane, eight port) PCI Express Gen 2-compliant switches includes a DMA engine in the devices that implement a descriptor ring approach, while each of the four DMA channels can saturate a x8 link at Gen 2 speeds (up to 4GB/s) in one direction. Each descriptor provides support for large transfer sizes (up to 128MB) giving the user the capability to perform very large data transfers in any direction (memory to device, device to device, memory to memory). Descriptors can exist in host memory or, alternatively, inside the DMA switch. Up to 256 descriptors are supported internally in each PLX DMA switch, which also support 32-bit and 64-bit transfers as well as programmable QoS. Read more: www.plxtech.com/about/news/pr/?y=2008&rel=0818 PCIe Packet Generators & Analyzers on a Budget
The PLX PEX 8624, PEX 8632, and PEX 8648 Gen 2 switch hardware Reference Design Kits (RDKs) are used to help engineers bring up designs quickly. However, these RDKs can also be configured into a PCIe Packet Generator. Although the limited capabilities of a Packet Generator can not completely replace a PCIe analyzer, the basic need to saturate a PCIe Gen 2 link is one of the many features of a PLX Gen 2 RDK. This Packet Generator proves to help engineers be more effective and time efficient when no PCIe analyzer is readily available. Any size, 4 bytes up to 2048 bytes, Memory Read and/or Memory Write TLP can be constructed. Engineers have the flexibility to specify a Memory Write sequence or have the software randomly generate data to be written. Also, the data could potentially be an incremental pattern if need be. Another option available is to interject any amount of clock delay in-between each TLP. Memory Reads and Memory Writes can be intertwined depending on the user defined sequence of events. Other features such as Performance Monitor and SerDes eye measurement, along with the Packet Generator help engineers save money by using less expensive tools and the ability to re-use RDKs across multiple projects. Download SDK: www.plxtech.com/sdk PLX Software Development Kit (SDK) 6.0 Now Released
With access support of this SDK, PLX Gen 2 devices have special features through the PEX Device Editor that allow users to do things like Performance Monitoring, checking SerDes Eye Width and operating the Packet Generator/Analyzer functions described in previous section of this newsletter. The PEX Device Editor also allows users to access devices through I2C. The utility also provide the user with a means to access a device's EEPROM, and perform several operations on the EEPROM. Combining the PLX SDK along with PLX RDK (rapid development kit) hardware will help customers get to market faster. During installation of the PLX SDK the installer will ask for a special alphanumeric key. This key can be obtained from your local PLX sales representative. Access to the full SDK feature-set depends on your NDA status with PLX. Download SDK: www.plxtech.com/sdk PCI Express Gen 2 Training - October 1st, Register Today
Available Sessions: AMD's Premium ATI Dual GPU Graphics Cards Feature PLX Switch
The ExpressLane™ PEX 8647 switch, now officially launched, is specifically designed for demanding graphics applications. The device is a 48-lane, three-port, PCI Express Gen 2 (5.0 GT/s)-compliant switch featuring large packet memory, low power management and cut-thru architecture for low latency - aspects that boost performance and are ideal for the cutting-edge graphics industry. The PEX 8647, with three x16 ports to allow for the optimal configuration of graphics applications, also offers PLX's unique array of performance-maximizing features such as Dual Cast™ which provides simultaneous copying of data from one ingress port to two egress ports, as well as a special software/hardware development kit that enables system designers to fine-tune and perform system diagnostics, thus accelerating the engineering design process. Read more: www.plxtech.com/about/news/pr/?y=2008&rel=0825 Low Cost, Low Lane Count Switch = Mass Market AppealThe PEX 8604 (four lanes, four ports), PEX 8606 (six lanes, six ports) deliver all the unique features available in their higher-lane-count siblings, including the exclusive PLX performancePAK™ and visionPAK™ suites, non-transparency ports, smallest package footprints, and low power requirements. These new low-lane-count PCIe Gen 2 switches are ideal for price-sensitive, mass-production market segments such as set-top boxes, DVRs and multi-function printers.
Read more: www.plxtech.com/about/news/pr/?y=2008&rel=0616 Special Control Plane Switches for Telecom, Networking
The three new devices including flexible port configurations (x1, x2, x4, x8), low power requirements (down to 1.1W), low latency (140ns), packaging as small as 15mm x 15mm, spread-spectrum clock isolation supporting dual-clock domains, and two virtual channels (VCs) per port ensuring quality of service (QoS) - all critical elements for successful PCIe connectivity on the control plane. Read more: www.plxtech.com/about/news/pr/?y=2008&rel=0414 The Road to Gen 3 is Feature RichGen 2 is now, while Gen 3 is on the horizon and will effectively double performance with the initial base specification slated for release in 2009. The Gen 3 specification will maintain its low power, backwards compatibility and low cost, so designers can confidently design in Gen 2 parts today to take advantage of all the new features found today. Designing with Gen 2 now can also future-proof next-generation architectures. According to the PCI-SIG, the PCIe 3.0 specification will also introduce a number of optimizations for enhanced signaling and data integrity, including transmitter and receiver equalization, PLL improvements, clock data recovery and channel enhancements for currently supported topologies.
The Gen 2 pipeline also has many more unannounced exciting features to be introduced in 2008 and 2009, and PLX customers will soon be able to take advantage of the newest technology found in our Gen 2 PCI Express switches. This upcoming family will include high lane count and high port count switches that will initially target Blade & Rack Servers as well as the Storage & Networking markets. Ask your local PLX Sales representative for more details if you have an NDA in place. Contact Sales: www.plxtech.com/contact PLX Products at a Glance - New Snapshot FlyerThis one page flyer lists all PLX products and their main attributes. The PDF shows all released PCI Express Switch and Bridge devices on one easy reference page, as well as all legacy PCI, I/O Accelerators and USB controllers on the backside. Get PDF Now On Demand Technical Support 24/7The PLX web-based technical support portal is your ticket to fast relief in problem resolution. We have built a large FAQ site with a broad range of immediate answers. In the event your request can not be found in the current knowledge base, simply enter a new case and our global support team will jump to action. The PLX support portal login can be found at the top of our www.plxtech.com home page or directly through this URL. Access PCI Express datasheets or update your PLX profile and newsletter subscriptions by logging in at http://www.plxtech.com/mydata/ Copyright 2008: PLX, ExpressLane, visionPAK and performancePAK are trademarks of PLX Technology Inc., PCI Express and PCIe are trademarks of the PCI-SIG. |
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PLX has announced three powerful new PCIe switch devices with an innovative architecture that features an integrated direct memory access (DMA) engine. Each switch provides four DMA channels to support the high data rates required in storage systems, servers, networking, control plane and embedded markets. By offloading the DMA function typically required of the processor, PLX's DMA capable switches increase system performance and create a wide range of new options for next-generation designs. 
Engineers on tight budgets and no access to costly Analyzers now have a new alternative to proofing systems. Transform a PLX RDK into a PCI Express Packet Generator. A key component when designing for the PCI Express protocol that is often overlooked is the PCIe analyzer. This vital piece of equipment allows engineers to examine and investigate the actual data passing through the PCIe bus or generate specific traffic patterns to validate how a device or Root Complex will react to a specific traffic pattern. There is no endpoint available in the market today which can fully saturate a PCIe Gen 2 (5.0 GT/s) link other than a PCIe analyzer. Unfortunately, the hefty price tag associated with the analyzer is often the reason why design engineers go without such an integral necessity.
The PLX SDK 6.0 contains special custom software for Windows & Linux host environments where the PLX chip is accessed across the PCI/PCIe bus. This package is provided for the debug phase of hardware development and also for development of custom applications. 
Join PLX for a live technical training session - online webcast - focusing on PCI Express Gen 2 technology fundamentals, design challenges, and usage applications of the PCI Express switch as a basic building block. This interactive session allows time for Q&A following the training.
PEX 8647 PCIe Gen 2 switch has been chosen to provide high-performance, peer-to-peer fan-out operation on AMD's (NYSE: AMD) new flagship ATI Radeon™ HD 4870 X2 Dual-GPU graphics card. The innovative, high-performance HD 4870 X2, recently released and targeting eager extreme-video game fans, offers superior graphics execution via the industry's fastest card utilizing two GPUs on a single board and further enhanced with ATI CrossfireX™ technology. 
PEX 8604 and PEX 8606 low-lane-count, low-power (0.8W typ.) switches include features such as non-transparency (NT), configurable port flexibility (x1 or x2), true peer-to-peer fan-out, and two virtual channels (VCs) per port that help ensure quality of service (QoS). All PLX Gen 2 (5GT/s) switches are fully backward-compatible with the PCIe Gen 1 (2.5GT/s) standard, allowing designers to reap the benefits of this higher-performance technology, even in Gen 1-based systems. Design engineers also benefit from the industry's most advanced software and hardware development kit (SDK/RDK) products developed specifically to support PLX silicon.
PEX 8618 (16 lanes, 16 ports), PEX 8614 (12 lanes, 12 ports) and PEX 8608 (eight lanes, eight ports) PCIe Gen 2 switches represent key configurations specified by leading telecommunications and networking designers.
While the PCI-SIG nails down the final details of the 3.0 spec, the PLX roadmap is already loaded with Gen 3 products and the team is working hard to get these unique devices quickly to market. But designers should keep aware of new developments in Gen 2 switches that are available today because it still has a healthy and strong roadmap within this cycle. The latest PLX switch products now incorporate several distinctive features such as NT (non-transparent ports), an internal DMA engine, numerous debug and analysis tools, Read Pacing, Dual Cast, and Dynamic Buffer Allocation. These powerful tools will enhance any design, save cost, lower your power and get you to market faster.