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PEX 8604

4 Lane, 4 Port PCI Express Gen 2 (5.0 GT/s) Switch, 15 x 15mm PBGA
The ExpressLane™PEX 8604 device offers 4 PCI Express Gen 2 (5.0 GT/s) lanes, which supports up to four ports. The switch conforms to the PCI Express Base Specification, rev 2.0. The PEX8604 is the industry’s smallest 4-lane Gen 2 device and it enables users with the ability to connect multiple PCI Express endpoints which are used in a variety of consumer and embedded applications including Multi-Function Printers, wireless ethernet modules, IO expansion modules, Express Card applications as well as other low power applications. The PEX 8604 boasts unsurpassed performance with its non-blocking architecture, capable of supporting both host-centric as well as true peer-to-peer traffic on its ports. The PEX 8604 supports x2 port width natively on the upstream port which allows it to interface directly and seamlessly to embedded processors commonly used in such applications. The PEX 8604 also features an on-chip Non-Transparent port for dual-host and failover applications, supports dual-clock domain operation by virtue of support for Spread Spectrum Clock (SSC) isolation as well as two Virtual Channels for enhanced QoS. The device is hardware configurable and/or software programmable, allowing users to tailor their port configurations and QoS operating characteristics to suit their application requirements. The PEX 8604 is offered in a 15 x 15mm 196-ball PBGA. This device is available in both leaded and lead-free packaging.
Supporting Documentation
- PCIe Technical Info & White Papers
- General PLX Product Documentation
- Support Documentation (Quality, FAQs, RoHS...)
Hot Applications
PEX 8604 Technical Documentation
| Document/Resources | Everyone Access | Requires Membership | Requires NDA | Description | Version | Date |
|---|---|---|---|---|---|---|
| Product Brief | Download | Product Overview | 1.0 | 12/08 | ||
| Part Numbers Listing | View HTML | Part Number, Listing and Compliance | -- | 09/06 | ||
| Data Book | Download | Detailed Technical Specifications | 0.90 | 12/08 | ||
| Design Notes | Download | Quick Start Hardware Design Guide | 1.1 | 12/08 | ||
| Download | PEX8604 Hardware Design Checklist | 0.95 | 08/08 | |||
| Download | Power Management Modes, PEX 8600 Products (white paper) | 1.0 | 04/08 | |||
| Download | Dual Cast, 8600 family feature (white paper) | 1.0 | 10/07 | |||
| Download | Read Pacing, 8600 family feature (white paper) | 1.0 | 10/07 | |||
| Download | Dynamic Buffer Pool, 8600 family feature (white paper) | 1.0 | 10/07 | |||
| Download | Error Recovery and Fencing Mechanisms (white paper) | 1.0 | 01/08 | |||
| Errata | Download | Silicon Errata List | 0.4 | 12/08 | ||
| Interoperability | Download | Interoperability Report | 1.0 | 11/08 | ||
| Application Notes | Download | Using Dual Cast feature of Gen 2 switches | 1.0 | 05/08 | ||
| Download | Gen 2 switch compatibility with Gen 1 devices | 1.0 | 05/08 |
PEX 8604 Development Tools
| Document/Resources | Everyone Access | Requires Membership | Requires NDA | Description | Version | Date |
|---|---|---|---|---|---|---|
| Signal Integrity Kit | Download | PLX Gen 2 Testing over “16 / 30” Tyco Comm Backplane (presentation) | 1.0 | 12/08 | ||
| Download | PCIe Receiver Equalization (white paper) | 1.0 | 12/08 | |||
| Download | PEX 86xx Gen 2 Switch Linkup Issue with Intel Tylersburg Platforms (white paper) | 1.0 | 12/08 | |||
| Download | Using PEX 8648 SMA based (SI) Card (white paper) | 1.0 | 12/08 | |||
| Download | PLX PCI Express over 30” of Legacy Backplane (white paper) | 1.0 | 07/08 | |||
| Rapid Development Kit (RDK) | Download | Hardware Reference Manual | 1.1 | 12/08 | ||
| Software Development Kit (SDK) | View HTML | Software Development Kit | -- | -- | ||
| BSDL | Download | Boundary Scan Description Language files | -- | 11/08 | ||
| HSPICE Model | Download | HSPICE Model | -- | 06/08 | ||
| OrCAD | Download | OrCAD Library Files for the PEX 8604 | 1.0 | 07/08 | ||
| Download | OrCAD Design Files for Add-in Card RDK | 1.0 | 07/08 |
