PEX 8648

PEX 8618  Lead Free  PCI-SIG Integrator's List

16 Lane, 16 Port PCI Express Gen 2 (5.0 GT/s) Switch, 19 x 19mm PBGA

The ExpressLane™ PEX 8618 device offers 16 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 16 flexible ports. The switch conforms to the PCI Express Base Specification, rev 2.0. The PEX 8618 architecture supports packet cut-thru with the industry's lowest latency of 140ns (x4 to x1) and offers two virtual channels for traffic prioritization in the system. This, combined with large packet memory (2048 byte maximum payload size) and non-blocking internal switch architecture, provide full line-rate on all ports. The PEX 8618 supports both host-centric as well as true peer-to-peer traffic. The PEX 8618 also features an on-chip Non-Transparent port for dual-host and failover applications and supports dual-clock domain operation by virtue of support for Spread Spectrum Clock (SSC) isolation. This switch is hardware configurable and software programmable, allowing users to tailor their port configurations and quality-of-service system needs to suit their application requirements. This device can be used in a wide variety of applications including control planes in the communications and networking markets, servers, storage systems, embedded systems, multi-function printers, network interface adapters, medical imaging systems, industrial-control systems and AMC cards. The PEX 8618 is offered in a 19 x 19mm 324-ball PBGA and is available in both leaded and lead-free packaging.

Page Index

Related Gen 1 Devices


Related Gen 2 Devices

PEX 8618 Technical Documentation

Document/Resources Everyone Access Requires Membership Requires NDA Description Version Date
Product Brief Download     Product Overview 1.0 12/08
Part Numbers Listing View HTML     Part Number, Listing and Compliance -- 09/06
Data Book     Download Detailed Technical Specifications 0.90 12/08
Design Notes     Download Quick Start Hardware Design Guide 1.1 12/08
    Download PEX8618 Hardware Design Checklist 0.95 08/08
    Download Power Management Modes, PEX 8600 Products (white paper) 1.0 04/08
    Download Dual Cast, 8600 family feature (white paper) 1.0 10/07
    Download Read Pacing, 8600 family feature (white paper) 1.0 10/07
    Download Dynamic Buffer Pool, 8600 family feature (white paper) 1.0 10/07
    Download Error Recovery and Fencing Mechanisms (white paper) 1.0 01/08
Errata     Download Silicon Errata List 0.4 12/08
Interoperability     Download Interoperability Report 1.0 11/08
Application Notes     Download Using Dual Cast feature of Gen 2 switches 1.0 05/08
    Download Gen 2 switch compatibility with Gen 1 devices 1.0 05/08

PEX 8618 Development Tools

Document/Resources Everyone Access Requires Membership Requires NDA Description Version Date
Signal Integrity Kit     Download PLX Gen 2 Testing over “16 / 30” Tyco Comm Backplane (presentation) 1.0 12/08
    Download PCIe Receiver Equalization (white paper) 1.0 12/08
    Download PEX 86xx Gen 2 Switch Linkup Issue with Intel Tylersburg Platforms (white paper) 1.0 12/08
    Download Using PEX 8648 SMA based (SI) Card (white paper) 1.0 12/08
    Download PLX PCI Express over 30” of Legacy Backplane (white paper) 1.0 07/08
Rapid Development Kit (RDK)     Download Hardware Reference Manual 1.0 10/08
    Download Base Board Hardware Reference Manual 1.0 10/08
Software Development Kit (SDK)     View HTML Software Development Kit -- --
BSDL     Download Boundary Scan Description Language files 1.0 06/08
HSPICE Model     Download HSPICE Model -- 06/08
OrCAD     Download OrCAD Library Files for the PEX 8618 1.0 05/08
    Download OrCAD Design Files for Add-in Card RDK 1.0 05/08

PEX 8618 Applications

Application Description Document
Communications Router/Switch PCIe Connectivity & Fan-Out ExpressApps #60
(PDF)