PEX 8632

PEX 8632  Lead Free  PCI-SIG Integrator's List

32-Lane, 12- Port PCI Express Gen 2 (5.0 GT/s) Switch, 27 x 27mm FCBGA

The ExpressLane™ PEX 8632 device offers 32 PCI Express Gen 2 (5.0 GT/s) lanes, capable of configuring up to 12 flexible ports. The switch conforms to the PCI Express Base Specification, rev 2.0. The 32-lane switch enables users to add scalable, high bandwidth, non-blocking interconnection to a wide variety of applications including servers, communications, storage, blade servers, and embedded systems. The PEX 8632 boasts the industry’s lowest 32-lane PCIe Gen 2 latency at 145ns and unsurpassed performance with its non-blocking architecture, capable of supporting both host-centric as well as true peer-to-peer traffic. The PEX 8632 also features an on-chip Non-Transparent port for dual-host and failover applications, as well as three on-chip Hot-Plug controllers, allowing users to implement single-chip solutions. The device is hardware configurable and software programmable, allowing users to tailor their port configurations and QoS operating characteristics to suit their application requirements. The PEX 8632 is offered in a 27 x 27mm 676-ball FCBGA. This device is available in lead-free packaging.

Page Index

Related Gen 1 Devices


Related Gen 2 Devices

PEX 8632 Technical Documentation

Document/Resources Everyone Access Requires Membership Requires NDA Description Version Date
Product Brief Download     Product Overview 0.96 10/08
Part Numbers Listing View HTML     Part Number, Listing and Compliance -- 09/06
Data Book     Download Detailed Technical Specifications 0.98 12/08
Design Notes     Download Quick Start Hardware Design Guide 1.1 10/07
    Download 8-Port Hardware Design Checklist 1.0 10/08
    Download 12-Port Hardware Design Checklist 1.0 10/08
    Download Power Management Modes, PEX 8600 Products (white paper) 1.0 04/08
    Download Dual Cast, 8600 family feature (white paper) 1.0 10/07
    Download Read Pacing, 8600 family feature (white paper) 1.0 10/07
    Download Dynamic Buffer Pool, 8600 family feature (white paper) 1.0 10/07
    Download Error Recovery and Fencing Mechanisms (white paper) 1.0 01/08
Errata     Download Silicon Errata List 0.92 11/08
Interoperability     Download Interoperability Report 1.0 10/08
Application Notes     Download Using Dual Cast feature of Gen 2 switches 1.0 05/08
    Download Gen 2 switch compatibility with Gen 1 devices 1.0 05/08

PEX 8632 Development Tools

Document/Resources Everyone Access Requires Membership Requires NDA Description Version Date
Signal Integrity Kit     Download PLX Gen 2 Testing over “16 / 30” Tyco Comm Backplane (presentation) 1.0 12/08
    Download PCIe Receiver Equalization (white paper) 1.0 12/08
    Download PEX 86xx Gen 2 Switch Linkup Issue with Intel Tylersburg Platforms (white paper) 1.0 12/08
    Download Using PEX 8648 SMA based (SI) Card (white paper) 1.0 12/08
    Download PLX PCI Express over 30” of Legacy Backplane (white paper) 1.0 07/08
Rapid Development Kit (RDK)     Download RDK Schematic 1.0 04/08
    Download RDK Hardware Reference Manual 1.1 11/08
Software Development Kit (SDK)     View HTML Software Development Kit -- --
BSDL     Download Preliminary Boundary Scan Description Language files 0.91 10/08
HSPICE Model     Download HSPICE Model 0.9 07/08
OrCAD     Download Preliminary OrCAD Library 0.91 03/08