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PCI Express Technology Information

General PCI Express & Implementation

Document / Resource Description Date Format
PLX PCI Express over 30" of Legacy Backplane (Requires NDA) This paper demonstrates the ability of PLX Gen 2 switches to link and operate with over 30 inches of a legacy Communication space (Tyco) backplane at both 2.5 and 5Gbps. In the communications space, the ability to drive distance and the ability to operate without a common clock reference are important factors for these systems. Both these conditions are set up and demonstrated. 07/08 Technology White Paper
Using the Dual Cast™ Feature on PEX 86xx Gen 2 PCI Express Switches (Requires NDA) This application note describes the functions and programming of the Dual Cast feature available on PLX PEX86xx series Gen 2 PCI Express switches. A typical system configuration and register programming example is also provided. 05/08 Application Note
Power Management Modes (8600 PCIe Gen 2 family) (Requires NDA) Given the importance of lower power consumption and the rapid rise in power requirements of ever-escalating circuit densities and operating frequencies, PLX has designed multiple power saving features that enable best-in-class power savings. 04/08 Technology White Paper
Error Recovery and Fencing Mechanisms (8600 PCIe Gen 2 family) (Requires NDA) The new devices take into the account the lack of ECRC support in the chipsets and implements mechanisms to mitigate error propagation close to the point of origin of error. Error Recovery and Fencing mechanisms have been enhanced to not allow a fatal error to propagate and cause system issues. 01/08 Technology White Paper
Dual Cast™ (8600 PCIe Gen 2 family) (Requires NDA) The Dual Cast feature of the PLX PEX 8600 family allows the switch to make a copy of a posted write packet and send it to a second address, saving the original source the trouble of transmitting the same data twice, to two different locations. 10/07 Technology White Paper
Read Pacing™ (8600 PCIe Gen 2 family) (Requires NDA) In read pacing, excess upstream read requests are delayed in the switch to avoid both blocking other device’s read requests in the RC and to limit completion queue size in the switch and can improve performance by >10x. 10/07 Technology White Paper
Dynamic Buffer Allocation (8600 PCIe Gen 2 family) (Requires NDA) Dynamic buffer allocation makes best use of available switch memory, leading to higher performance and/or lower cost. 10/07 Technology White Paper
Overcoming Latency in PCIe Systems using PLX Overcoming PCI Express latency isn't simply a matter of choosing the lowest-latency components from among those suitable for an embedded-system design, but it's a good place to start.  It's also a matter of architecting operations to reduce or eliminate the sensitivity of system performance to latency. The availability of low-latency switches from PLX Technology makes the job of everyone producing a PCIe-based infrastructure easier.  These industry-leading switches drop latency to as low as 110ns, or 87 percent lower than competing devices on the market.  Low-latency switches such as these should be the first choice of system engineers interested in producing high-performance systems. 09/07 Technology White Paper
PLX PCIe Switch Power Consumption Explained The power consumption of silicon with high-speed SerDes depends on the following factors. 12/07 Technology White Paper
PCI Express Packet Latency Matters Latency is the delay between starting and completing an action. For a switch, it’s the time between the first bit of a packet on an input pin and the first bit of that packet on an output pin forwarded through the switch. 01/07 Technology White Paper
Choosing PCI Express Packet Payload Size This white paper gives guidelines to device designers based upon consideration of protocol efficiency and market requirements. 01/07 Technology White Paper
On Chip Standard Hot-Plug Controller PLX Technology has taken the on-chip integrating approach for SHPC support on all of its PCIe switches. 01/07 Technology White Paper
Checking PCIe Switch Performance in an Ethernet Network Example of a PCI Express host running a Gigabit Ethernet network. A PLX switch is added to the network and the resultant system degradation is tested. 01/07 Technology White Paper
Tight vs. Loose Coupling of Differential Pairs for PCI Express Early adopters of PCI Express technology have completed a number of board designs for their new products. One of the challenges of these designs is laying out the PCI Express differential lanes as tightly coupled pairs. 03/06 Conference Presentation
Don't Let PCI Express Leave the Station Without You Converting PCI Add-in Cards to PCI Express 12/05 Webcast
Non-Transparent Bridging Simplified Multi-Host System and Intelligent I/O Design with PCI Express 04/05 Technology Brief
Using Non-Transparent Bridging in PCI Express Systems: Enabling Multi-Processor Systems PCI Express technology provides a number of benefits including the ability to increase processing bandwidth, provide extensive data integrity, and true quality of service. To fully realize its potential, this new standard also needs to address multi processor designs and provide redundancy. Now PCI Express technology, like its predecessors PCI and PCI-X, has incorporated industry standard non transparent bridging techniques. This paper explains how this non transparency allows the implementation of multi-host systems and provides host failover support. 06/04 Technology White Paper
Enabling Multi-Host System Designs with PCI Express Technology An overview of the more in-depth white paper titled: Using Non-Transparent Bridging in PCI Express Systems: Enabling Multi Processor Systems 05/04 Technology White Paper
PCI Express Technology Overview An introduction to the PCI Express protocol and how this interconnect technology fits into today's environment. 09/03 Technology White Paper

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